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| 1/22 september 2001 st70137 hardware features n support digital signal processing requirements for one adsl cpe chanel (itu-r) n compliant with itu 992.1 (adsl full rate) annexe a (adsl over pots) and annexe b (adsl over isdn) and itu 922.2 (g.lite) and ansi t1.413. n direct interface to pci bus (pci release 2.2 and compliant with microsoft pc99 & pc2001 specifica- tion) n direct interface to usb (usb release 1.1 specification) n direct interface to the external serial memory to support pci/usb user's configuration n direct analog front end interface for st70136 or st70134 n 4 to 8 gpio depending on selected afe and external memory configu- ration used n clock & reset interface n 1.8v and 3.3v power supply n ttl logic levels compatible (depending on pads) n power management n low power consumption : 0.4w n tqfp 144 st70137 software features n rfc 2364 ppp over atm n uni 3.0, 3.1, 4.0 signaling n ubr, cbr n aal0, aal5 n ndis5.0 pci driver and usb driver description st70137 is stmicroelectronics unicorn tm chipset adsl dmt transceiver for controllerless adsl cpe modem. unicorn tm allows to develop easily and quickly low cost adsl cpe modem for pc environment. unicorn tm is made of two devices, st70137 and st70136 or st70134 (cpe adsl analog front end). st70137 provides pci and usb interface. pci is used to build adsl cpe modem bundled in the pc, usb interface is used to build external bus powered adsl modem. st70137 is compliant with itu 992.1 annexe a and b, with itu 992.2 and with ansi t1.413. unicorn tm chipset is delivered with a complete pc software suite for microsoft windows 98, windows 2000 and windows nt. ndis5.0 pci driver and usb driver with adsl modem control and atm device driver are provided assuring full atm support. configuration and diagnostic tools are also provided. unicorn tm chipset and pc software ensure interoperability with the most deployed dslam. tqfp144 order code: ST70137TQFP st70137 unicorn tm pci & usb controllerless adsl dmt transceiver
st70137 2/22 typical application block diagram obc: on board controller tgb: time generation block tap: test access protocol utop fsm: utopia finite state machine pc pci usb or st70137 dmt st70136 afe or st70134 line i/f pots line usb dongle modem or pci board pots line adsl modem st70137 st70136 or st70134 usb_bridge pci_bridge cfg_mems bridge switcher usb_pcin_sel tgb atm fifos obc fifos regs peripheral utop fsm obc_if adsl up tosca v. 2.0 tap afe if cfg_sel clk rst gpio if usb if pci_if mem if st70137 3/22 software architecture user applications: netscape, netmeeting, etc. trace tools ring 3: user mode ndis 5 control data modem sw win32 kernel hw abstraction layer usb driver pci driver registry uhcd.sys ohcd.sys usbd sys - ms bus driver uhci (intel) ohci (nec and others) usb device pci device ring 0: kernel level hardware st70137 4/22 pin connections pci_ad[15] 144 143 142 141 140 139 138 137 136 135 133 132 131 130 129 128 127 126 125124 123 122 121120 119 118 117116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 134 vdd 3.3 gpio[0] gpio[1] gpio[2] gpio[3] vss dminus dplus vss rstn cfg_sce cfg_sck/ gpio[6] cfg_sdi cfg_sdo/gpio[7] vdd 1.8 c_ext vss vdd 3.3 vr50f pci_intan pci_rstn vss pci_clk pci_gntn vdd 3.3 pci_reqn pci_pmen vss pci_ad[31] pci_ad[30] vdd 3.3 pci[ad29] pci_ad[28] vss pci_ad[27] pci_ad[26] 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 vdd3.3 actd pwdn suspendn suspend ld_pwdn vss afesel usb_pcin_sel c fg_mem_sel v aux_d_usb_sp vdd1.8 vr50 pci_ad[0] pci_ad[1] pci_ad[2] vdd3.3 pci_ad[3] pci_ad[4] vss pci_ad[5] pci_ad[6] vdd3.3 pci_ad[7] pci_cbe0n vss pci_ad[8] pci_ad[9] vdd3.3 pci_ad[10] pci_ad[11] vss pci_ad[12] pci_ad[13] vdd3.3 pci_ad[14] d_vss_pll d_vdd_pll a_vss_pll a_vdd_pll vss trstb tck tms tdo tdi vdd1.8 vss vss ctrldin / gpio[4] ctrldout afewr/ gpio[5] clwd vdd3.3 mclk vss comp_rout vdd1.8 aferxd[3] aferxd[2] aferxd[1] aferxd[0] vss afetxd[3] afetxd[2] afetxd[1] afetxd[0] vss aferst vss vss vss st70137 vdd3.3 pci_ad[25] pci_ad[24] vss pci_cbe3n pci_idsel vdd3.3 pci_ad[23] pci_ad[22] vss pci_ad[21] pci_ad[20] vdd3.3 pci_ad[19] pci_ad[18] vss pci_ad[17] pci_ad[16] vdd3.3 vdd1.8 pci_cbe2n pci_framen vss pci_irdyn pci_trdyn vdd3.3 pci_devseln pci_stopn vss perrn serrn vdd3.3 pci_par pci_cbe1n vss st70137 5/22 pin list pin name type drive description 1 vdd3.3 p power supply pins 3.3v for i/o pads (not pci) 2 gpio[0] i/o 4ma 3 gpio[1] i/o 4ma 4 gpio[2] i/o 4ma 5 gpio[3] i/o 4ma 6 vss p ground 7 data_minus i/o 8 data_plus i/o 9 vss p ground 10 rstn i 11 cfg_sce o 4ma 12 cfg_sck/gpo[ 6] o 4ma 13 cfg_sdi i 14 cfg_sdo/gpo[ 7] o 4ma 15 vdd 1.8 p power supply pins 1.8v for core 16 c_ext p external capacitor to reduce ripple of the internal dc regulator 1 17 vss ground 18 vdd3.3 p power supply pins 3.3v for pci i/o pads esd protection 19 vr50f p power supply for dc regulator (3.3v) 20 pci_intan od 8ma low, high impendance 21 pci_rstn i 22 vss p ground 23 pci_clk i 24 pci_gntn i 25 vdd3.3 p power supply pins 3.3v for pci i/o pads esd protection 26 pci_reqn o 8ma 27 pci_pmen od 8ma 28 vss p ground 29 pci_ad[31] i/o 8ma 30 pci_ad[30] i/o 8ma 31 vdd3.3 p power supply pins 3.3v for pci i/o pads 32 pci_ad[29] i/o 8ma 33 pci_ad[28] i/o 8ma 34 vss p ground note 1. pin c_ext must be connected: 10nf 1 m f st70137 6/22 35 pci_ad[27] i/o 8ma 36 pci_ad[26] i/o 8ma 37 vdd3.3 p power supply pins 3.3v for pci i/o pads esd protection 38 pci_ad[25] i/o 8ma 39 pci_ad[24] i/o 8ma 40 vss p ground 41 pci_cbe_n[3] i/o 8ma 42 pci_idsel i 43 vdd3.3 p power supply pins 3.3v for pci i/o pads esd protection 44 pci_ad[23] i/o 8ma 45 pci_ad[22] i/o 8ma 46 vss p ground 47 pci_ad[21] i/o 8ma 48 pci_ad[20] i/o 8ma 49 vdd3.3 p power supply pins 3.3v for pci i/o pads esd protection 50 pci_ad[19] i/o 8ma 51 pci_ad[18] i/o 8ma 52 vss p ground 53 pci_ad[17] i/o 8ma 54 pci_ad[16] i/o 8ma 55 vdd3.3 p power supply pins 3.3v for pci i/o pads 56 vdd1.8 p power supply pins 1.8v for core 57 pci_cbe_n[2] i/o 8ma 58 pci_framen i/o 8ma 59 vss p ground 60 pci_irdyn i/o 8ma 61 pci_trdyn i/o 8ma 62 vdd3.3 p power supply pins 3.3v for pci i/o pads esd protection 63 pci_devseln i/o 8ma 64 pci_stopn i/o 8ma 65 vss p ground 66 pci_perrn i/o 8ma 67 pci_serrn i/o 8ma 68 vdd3.3 p power supply pins 3.3v for pci i/o pads esd protection 69 pci_par i/o 8ma 70 pci_cbe_n[1] i/o 8ma 71 vss p ground 72 pci_ad[15] i/o 8ma 73 pci_ad[14] i/o 8ma pin name type drive description pin list (continued) st70137 7/22 74 vdd3.3 p power supply pins 3.3v for pci i/o pads esd protection 75 pci_ad[13] i/o 8ma 76 pci_ad[12] i/o 8ma 77 vss p ground 78 pci_ad[11] i/o 8ma 79 pci_ad[10] i/o 8ma 80 vdd3.3 p power supply pins 3.3v for pci i/o pads esd protection 81 pci_ad[9] i/o 8ma 82 pci_ad[8] i/o 8ma 83 vss p ground 84 pci_cbe_n[0] i/o 8ma 85 pci_ad[7] i/o 8ma 86 vdd3.3 p power supply pins 3.3v for pci i/o pads 87 pci_ad[6] i/o 8ma 88 pci_ad[5] i/o 8ma 89 vss p ground 90 pci_ad[4] i/o 8ma 91 pci_ad[3] i/o 8ma 92 vdd3.3 p power supply pins 3.3v for pci i/o pads esd protection 93 pci_ad[2] i/o 8ma 94 pci_ad[1] i/o 8ma 95 pci_ad[0] i/o 8ma 96 vr50 p 3.3v power supply for dc regulator 97 vdd1.8 p power 98 vaux_d/usb_sp i 99 cfg_mem_sel i 100 usb_pcin_sel i 101 afesel i 102 vss p ground 103 lpdwdn o 4ma 104 suspend o 4ma 105 suspendn o 4ma 106 pwdn o 4ma 107 actd i 108 vdd3.3 p power supply pins 3.3v for i/o pads (not pci) 109 test i/o test reserved - must be fixed to ground 110 test i/o test reserved - must be fixed to ground 111 test i/o test reserved - must be fixed to ground 112 aferst o 4ma pin name type drive description pin list (continued) st70137 8/22 113 vss p ground 114 afetxd[0] o 8ma 115 afetxd[1] o 8ma 116 afetxd[2] o 8ma 117 afetxd[3] o 8ma 118 vss p ground 119 aferxd[0] i 120 aferxd[1] i 121 aferxd[2] i 122 aferxd[3] i 123 vdd1.8 p power supply pins 1.8v for core 124 comp_cell o compensation cell resistor 1 125 vss p ground 126 mclk i 127 vdd3.3 p power supply pins 3.3v for i/o pads (not pci) 128 clwd i 129 afewr/gpio[5] i/o 4ma 130 ctrldout o 4ma 131 ctrldin/gpio[4] i/o 4ma 132 vss p ground 133 test i/o test reserved - must be fixed to ground 134 vdd1.8 p power supply pins 1.8v for core 135 tdi i 136 tdo o 4ma 137 tms i 138 tck i 139 trstb i 140 vss p ground 141 vdd_apll p pll analog power supply 1.8v 142 vss_apll p pll analog ground 143 vdd_dpll p pll digital power supply 1.8v 144 vss_dpll p pll digital ground pin name type drive description pin list (continued) note 1. note: pci section from pin 16 to pin 96 (included): all the power supply pins (at 3.3v) included in this section are intented for pci i/o pads. comp_cell 100k w 1% st70137 9/22 pin description signal name direction init status polarity signal description pci interface pci_clk i - - pci clock. (33 mhz) the rising edge of this signal is the reference upon which all the other pci signals are based except for pci_rstn and pci_intan. the maximum pci_clk frequency for st70137 is 33mhz and the minimum is dc. pci_rstn i i l pci reset reset bring st70137 in a known state: - all pci bus output signal tri-stated - all open drain signals floated - all registers set to their factory defaults - all fifos emptied - gpio signals tri-stated - sachem macrocell initialized - clock of adsl_up stopped - afe set in power down mode pci_reqn o h l pci request this signal is sourced by an agent wishing to become a bus master. it is a point to point signal and each master has its own pci_reqn. pci_gntn i i l pci grant the pci_gntn signal is a dedicated, point-to-point signal provided to each potential bus master and signifies that access to the bus has been granted. pci_ad[31:0] i/o i - pci multiplexed address/data bus address and data are multiplexed on the same pci bus pins. a pci bus transaction consists of an address phase followed by the one or more data phase. an address phase occurs on the pclk cycle in which pci_framen is asserted. a data phase occurs on pclk cycles in which pci_irdyn and pci_trdyn are both asserted. st70137 10/22 pci_cbe_n[3:0] i/o i l pci multiplexed bus command mode bus command and byte enables are multiplexed on the same pins. these pins define the current bus command during an address phase. during a data phase, these pins are used as byte enables, with pci_cbe_n[0] (lsb) enabling byte 0 and pci_cbe_n[3] enabling byte 3 (msb). c/be[3:0]=command type 0000 = interrupt acknowledge 0001 = special cycle 0010 = i/o read 0011 = i/o write 0100 = reserved 0101 = reserved 0110 = memory read 0111 = memory write 1000 = reserved 1001 = reserved 1010 = configuration read 1011 = configuration write 1100 = memory read multiple 1101 = memory write multiple 1110 = memory read line 1111 = memory write and invalidate pci_par i/o i h pci parity (even) parity is always driven as even from all pci_ad[31:0] and pci_cbe[3:0] signals. the parity is valid during the clock following the address phase and is driven by the bus mas- ter. during a data phase for write transactions, the bus master sources this signal on the clock following pci_irdyn active; during data phase for read transac- tions, this signal is driven by the target and is valid on the clock following pci_trdyn active. the pci_par signal has the same timing as pci_ad[], delayed by one clock. pci_framen i/o i l pci cycle frame this signal is driven by current bus master to indicate the beginning and duration of a bus transaction. when pci_framen is first asserted, it indicates a bus transac- tion is beginning with a valid addresses and bus com- mand present on pci_ad[31:0] and pci_cbe[3:0]. data transfer continue until pci_framen is asserted. pci_framen de-assertion indicates the transaction is in final data phase or has completed. pci_devseln i/o i l pci device select this signal is driven by a target decoding and recognizing its bus address. this signal informs a bus master whether an agent has decoded a current bus cycle. pci_irdyn i/o i l pci initiator ready this signal is always driven by the bus master to indicate its ability to complete the current data phase. during write transactions it indicates pci_ad[] contains valid data. pci_idsel i i h pci initializatio n device select this pin is used as chip select during configuration read or write transactions. signal name direction init status polarity signal description pin description (continued) st70137 11/22 pci_trdyn i/o i l pci target ready this signal is driven by the select target to indicate the tar- get is able to complete the current data phase. during read transactions, it indicates pci_ad[] contains valid data. wait states occur until both pci_trdyn and pci_irdyn are asserted togheter. pci_perrn i/o i l pci parity error only for reporting data parity errors for all bus transactions except for special cycles. it is driven by the agent receiving data two clock cycles after the parity was detected as an error. this signal is driven inactive (high) for one clock cycle prior to returning to the tri-state condition. pci_serrn o z l pci system error used to report address and data parity errors on special cycle commands and any other error condition having a catastrophic system impact. pci_intan o z l pci interrupt a this signal is defined as optional and level sensitive. driv- ing it low will interrupt to the host. the pci_intan inter- rupt is to be used for any single function device requiring an interrupt capability. pci_pmen o z l pci power management event this signal is used to indicate that a power management event has been detected. the pci_pmen signal is asyn- chronous with respect to the pci clock; it is set (if enabled) by the low to high transition of the actd signal. pci_stopn i/o i l pci stop this signal indicates the current target is requesting the master to stop the current transaction. usb interface dplus i/o i + differential positive usb data input/output. dminus i/o i - differential negative usb data input/output. miscellaneous interface gpio[3:0] i/o i - general purpose i/o bus these signals are controlled by internal registers located inside adsl up block. at the power-up, hardware or software reset the input direction is chosen. cfg_mem_sel i i - select internal [1] or external [0] pci/usb configuration memory. usb_pcin_sel i i - select pci [0] or usb [1] interface selecting usb interface and if all test pins are set to default value, all the pci pads are deactivated. the power supply for this section can be not provided. the pci section is frozen. selecting pci interface the dminus and dplus has to be set to the low level (reset mode). the pll is in power down and no any clock will be provided to the usb section. vaux_d / usb_sp i i - vaux detect when usb_pcin_sel = [0] or usb self powered when usb_pcin_sel = [1]. signal name direction init status polarity signal description pin description (continued) st70137 12/22 clock & reset interface mclk i i - 35.328 mhz master input clock. rstn i i l asynchronous master input reset (active if usb_pci_sel = `1'). afe interface afetxd[3:0] o l - afe transmit data nibble bus the signal changes are synchronized to the rising edge of mclk clock signal. aferxd[3:0] i i - afe receive data nibble bus the signal changes are synchronized to the rising edge of mclk clock signal. clwd i i h start of word indication this signal is the word clock used to enable shift of data. it occurs on ctrldout signal to indicate the first data of the nibble sequence. the clwd frequency is equal to mclk/4. ctrldout o h l transmit control word data to afe the data is shifted out from internal register on the rising edge of mclk during clwd assertion. afesel i i - select st-70136 [0] or adsl_c [1]. aferst o l l afe reset this signal is connected to the internal pcfw (usb_pcin_sel = [0]) or ucfw registers (usb_pcin_sel = [1]) if afesel = [0], or to the sachem gpout register if afesel = [1]. not usable in usb mode. afewr / gpio[ 5] i/o i l/- afe write control output signal (afesel = 0), or gen- eral purpose i/o pin. the selection is performed writing the proper bit in the pcfw or ucfw (depending on sta- tus of usb_pcin_sel pin) registers. at the power-on or hardware reset the gpio[5] function is selected. ctrldin / gpio[4] i i l/- receive control word data from afe (afesel = 0), or general purpose i/o pin. the selection is performed writ- ing the proper bit in the pcfw or ucfw (depending on status of usb_pcin_sel pin) registers. at the power-on or hardware reset the gpio[4] function is selected actd i i h activation tone detect [1] (or wake up signal). when pci if has been selected, the low to high transi- tion of actd asserts the pci_pmen signal (if this last has been enabled) and generates an interrupt event. when usb if has been selected, the low to high transi- tion of actd de-asserts the suspend signal and re-enable the internal st70137 activity. suspend o l h suspend mode indication. suspendn o h l suspend mode indication negated. pwdn o h h afe power down. ldpwdn o h h line driver power down [1]. signal name direction init status polarity signal description pin description (continued) st70137 13/22 test condition all ouputs have been loaded with. * see text scheme at page 20. cfg_mem interface cfg_sce o l h chip enable this pin is designed to directly interface to a serial eeprom that use the 93c66 eeprom interface proto- col. this pin has to be connected directly to the eeprom's chip select pin. cfg_sck/gpo[ 6] o l - serial clock or general purpose output pin 6 depending on the internal selection. the selection is performed writ- ing the proper bit inside the pcfw or ucfw register. at the power-on or hardware reset the cfg_clk functional- ity is selected. this pin is designed to directly interface to a serial eeprom that use the 93c66 eeprom interface protocol. cfg_sdi i i h serial data input data going into this pin has to be generated on the rising edge of cfg_sck. this pin is designed to directly inter- face to a serial eeprom that use the 93c66 eeprom interface protocol. cfg_sdo/gpo[ 7] o l - serial data/address output general purpose output pin 7 depending on the internal selection. the selection is performed writing the proper bit inside the pcfw or ucfw register. at the power-up or hardware reset the cfg_sdo functionality is selected. the cfg_sdo data change is synchronous with the fall- ing edge of cfg_sck. this pin is designed to directly interface to a serial eeprom that use the 93c66 eeprom interface protocol. jtag interface tdi i ih - jtag test data input. tdo o - - jtag test data output. tms i ih l jtag test mode select. tck i il - jtag test clock. trstb i il l jtag reset (active low). outputs minimum maximum unit pci 0 50 pf usb * 0 50 pf others 0 15 pf signal name direction init status polarity signal description pin description (continued) st70137 14/22 timing specification afe if transmit & receive signals mclk master clock symbol parameter minimum typical maximum unit f clock frequency 35.328 mhz t clock period 28.3 ns th clock duty cycle 40 60 % afe if transmit & receive signals ts1 data setup time 5 ns th1 data hold time 7 ns tv1 data valid time 13 ns t s2 data setup time 5 ns t h2 data hold time 6 ns t v2 data valid time 18 ns t s3 data setup time 20 ns t h3 data hold time 1 ns tv3 data valid time 18 ns mclk ts1 th1 tv1 th2 ts2 tv2 ts3 th3 aferxd afetxd clwd ctrldout ctrldin afewr tv3 t st70137 15/22 cfg_mem if signals with pci = 30.3ns gpio if cfg_mem if signals with pci = 30.3ns * symbol parameter minimum typical maximum unit ts data setup time 45 ns th data hold time 0 ns tv1 data valid time 970 ns tv2 data valid time 160 ns tsck sck clock period: - usb 48mhz usb_clk / 64 ns - pci 33mhz pci_clk / 64 * pci conditions are more restrictive than usb conditions. gpio if symbol parameter minimum typical maximum unit tv output data valid from pci_clk 22 ns cfg_sck cfg_sdo cfg_sdi cfg_sce ts th tv1 tv2 tsclk pci_clk gpio output tv st70137 16/22 electrical specifications absolute maximum ratings pci interface dc specifications * guaranted by design. usb interface dc specifications nominal dc characteristics (dplus, dminus) * guaranted by design. parameter description minimum typical maximum units v dd 3.3 supply voltage 3.0 3.3 3.6 v v dd 1.8 supply voltage 1.62 1.8 1.98 v ptot total power dissipation 450 mw tamb ambient temperature 1.5ml airflow 0 70 c tstg storage temperature -65 +150 c v esd esd protection (hbm) 2000 v parameter description condition minimum typical maximum units vilp input low voltage -0.5 0.3v dd v vihp input high voltage 0.5v dd v dd +0.5 v lip input leakage current 0 st70137 18/22 pci clock waveform 5v pci clock waveform 3.3v pci timings * pci reqn and gntn are point-to-point signals and have different output valid delay and input setupt times than do bused signals. reqn has set up of 12ns and gntn of 10ns. all other signals are bused. ** guaranted by design. symbol parameter minimum typical maximum units tval clock to signal valid delay (bused signals) 2 11 ns tval(ptp) clock to signal valid delay (point to point) 2 12 ns ton float to active delay 2 ns toff active to float delay 28 ns tsu input set up time to clock (bused signals) 7 ns tsu(ptp) input set up time to clock (point to point) * 10, 12 * ns th input hold time from clock 0 ns trst reset active time after power stable 1 ms trst-clk reset active time after clk stable ** 100 m s trst-off reset active to output float delay ** 40 ns 2.0v 1.5v 0.8v 2.4v 0.4v tc th ti 0.5v dd 0.4v dd 0.3v dd 0.6v dd 0.2v dd tc th ti st70137 19/22 usb interface ac specifications (1.1 version) ac characteristics (d+, d-) usb test scheme symbol parameter test conditio n minimum typical maximum units t dr average bit rate (12 m/s 0.05%) 11.97 12.03 mbps t r rise time between 10% and 90% (see figure rise and fall time measures) 420ns t f fall time 10% and 90% (see figure rise and fall time measures) 420ns v crs output signal crossover voltage 1.3 2 v clk th input output tri-state output tsu tval ton toff 1 2 test 50pf 50pf test st70137 20/22 rise and fall time measures input / output ttl generic characteristics the value presented in the following table apply for all ttl inputs and/or outputs unless otherwise specified. * guaranted by design. note: the reference current is dependent on the exact buffer chosen and is a part of the buffer name. the available values are 2, 4 and 8ma. symbol parameter test condition minimum typical maximum units v il low level input voltage 0.8 v v ih high level input voltage 2.0 v v ilhy low level threshold, falling * slow edge < 1v/ m s 0.9 1.35 v v ihhy low level threshold, rising * slow edge < 1v/ m s 1.3 1.9 v v hy schmitt trigger hysteresis * slow edge < 1v m s 0.4 0.7 v v ol low level output voltage i out = xma (see note) 0.4 v v oh high level output voltage i out = xma (see note) 2.4 v t f t r 90% 10% 10% 90% st70137 21/22 package mechanical data (tqfp144 - 20 x 20 x 1.40 mm) dimension millimeters inches minimum typical maximum minimum typical maximum a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.0067 0.0087 0.011 c 0.09 0.20 0.0035 0.008 d 22.00 0.866 d1 20.00 0.787 d3 17.50 0.689 e 0.50 0.020 e 22.00 0.866 e1 20.00 0.787 e3 17.50 0.689 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k0 (min.), 7 (max.) c b a1 a2 a l k l1 0,25 mm .010 inch gage plane 0.03 inch seating plane 0,076 mm 144 109 e 37 72 1 36 73 108 d3 d1 d e3 e1 e information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this pub lication are subject to change without notice. thi s pub lication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom - united states http ://www.st.com 22/22 st70137 st70137.pdf |
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